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rev. 0.3 8/07 copyright ? 2007 by silicon labora tories SI8430/31/35 SI8430/31/35 t riple -c hannel d igital i solator features applications safety regulatory approvals description silicon lab's family of digital isol ators are cmos devices that employ an rf coupler to transmit digital information across an isolation barrier. very high speed operation at low power levels is achieved. these parts are available in a 16-pin wide body soic package. three speed grade options (1, 10, 150 mbps) are available and achieve typical propagation delay of less than 10 ns. block diagram high-speed operation: dc ? 150 mbps low propagation delay: <10 ns wide operating supply voltage: 2.375-5.5v low power: i1 + i2 < 12 ma/channel at 100 mbps precise timing: 2 ns pulse width distortion 1 ns channel-channel matching 2 ns pulse width skew 2500 v rms isolation transient immunity: >25 kv/s tri-state outputs with enable control dc correct no start-up init ialization required <10 s startup time high temperature operation: 125 c at 100 mbps 100 c at 150 mbps wide body soic-16 package isolated switch mode supplies isolated adc, dac motor control power factor correction systems ul recognition:2500 v rms for 1 minute per ul1577 csa component acceptance notice vde certification conformity iec 60747-5-2 (vde0884 part 2) si8431 b1 a1 a3 a2 b3 b2 SI8430/35 a1 a3 a2 b3 b2 b1 nc en1 en2/nc en2 pin assignments wide body soic v dd1 gnd1 a1 a3 nc en1/nc gnd1 a2 1 2 3 4 5 6 7 8 top view v dd2 gnd2 b2 b1 nc b3 gnd2 en2/nc 9 12 11 10 13 14 15 16
SI8430/31/35 2 rev. 0.3
SI8430/31/35 rev. 0.3 3 t able of c ontents section page 1. electrical specificat ions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 2. typical performance characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3. application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 3.1. theory of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.2. eye diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 9 4. layout recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.1. supply bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.2. input and output characte ristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.3. enable (en1, en2) inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4.4. rf radiated emissions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.5. rf immunity and comm on mode transient im munity . . . . . . . . . . . . . . . . . . . . . . . 24 5. pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 6. ordering guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 7. package outline: wide body soic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 document change list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 contact information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
SI8430/31/35 4 rev. 0.3 1. electrical specifications table 1. electrical characteristics (v dd1 = 5 v, v dd2 = 5 v, t a = ?40 to 125 oc) parameter symbol test condition min typ max unit high level input voltage v ih 2.0 ? ? v low level input voltage v il ??0.8v high level output voltage v oh loh = ?4 ma v dd1 ,v dd2 ?0.4 4.8 ? v low level output voltage v ol lol = 4 ma ? 0.2 0.4 v input leakage current i l ??10a enable input high current i enh v enx = v ih ?4?a enable input low current i enl v enx = v il ?20?a dc supply current (all inputs 0 v or at supply) SI8430/35-a,-b,-c, v dd1 all inputs 0 dc ? 7 10 ma SI8430/35-a,-b,-c, v dd2 all inputs 0 dc ? 6 9 ma SI8430/35-a,-b,-c, v dd1 all inputs 1 dc ? 14 18 ma SI8430/35-a,-b,-c, v dd2 all inputs 1 dc ? 6 9 ma si8431-a,-b,-c, v dd1 all inputs 0 dc ? 8 12 ma si8431-a,-b,-c, v dd2 all inputs 0 dc ? 10 15 ma si8431-a,-b,-c, v dd1 all inputs 1 dc ? 13 19 ma si8431-a,-b,-c, v dd2 all inputs 1 dc ? 12 17 ma 10 mbps supply current (all inputs = 5 mhz square wa ve, ci = 15 pf on all outputs) SI8430/35-b,-c, v dd1 ?1115ma SI8430/35-b,-c, v dd2 ?1317ma si8431-b,-c, v dd1 ?1216ma si8431-b,-c, v dd2 ?1317ma 100 mbps supply current (all inputs = 50 mhz square wave, ci = 15 pf on all outputs) SI8430-c, v dd1 ?1115ma SI8430-c, v dd2 ?2328ma si8431-c, v dd1 ?1318ma si8431-c, v dd2 ?2126ma
SI8430/31/35 rev. 0.3 5 timing charac teristics si843x-a maximum data rate 0 ? 1 mbps minimum pulse width ? ? 1000 ns propagation delay t phl , t plh see figure 2 ? ? 75 ns pulse width distortion |t plh - t phl | pwd see figure 2 ? ? 30 ns propagation delay skew 1 t psk(p-p) ? ? 50 ns channel-channel skew t psk ? ? 40 ns si843x-b maximum data rate 0 ? 10 mbps minimum pulse width ? ? 100 ns propagation delay t phl , t plh see figure 2 ? ? 35 ns pulse width distortion |t plh - t phl | pwd see figure 2 ? ? 7.5 ns propagation delay skew 1 t psk(p-p) ? ? 25 ns channel-channel skew t psk ??5ns si843x-c maximum data rate 0 ? 150 mbps minimum pulse width ? ? 6.6 ns propagation delay t phl , t plh see figure 2 4 6.5 9.5 ns pulse width distortion |t plh - t phl | pwd see figure 2 ? ? 3 ns propagation delay skew 1 t psk(p-p) ??5.5ns channel-channel skew t psk ??3ns table 1. electrical characteristics (continued) (v dd1 = 5 v, v dd2 = 5 v, t a = ?40 to 125 oc) parameter symbol test condition min typ max unit
SI8430/31/35 6 rev. 0.3 figure 1. enable timing diagram figure 2. propagation delay timing for all models output rise time t r c l = 15 pf see figure 2 ?2?ns output fall time t f c l = 15 pf see figure 2 ?2?ns common mode transient immunity ctmi v i =v dd or 0 v 25 30 ? kv/s enable to data valid t en1 see figure 1 ? 5 ? ns enable to data tri-state t en2 see figure 1 ? 5 ? ns start-up time 2 t su ?3?s notes: 1. t psk(p-p) is the magnitude of the difference in propagation delay times measured between differ ent units operating at the same supply voltages, load, and ambient temperature. 2. start-up time is the time period from the applic ation of power to valid data at the output. table 1. electrical characteristics (continued) (v dd1 = 5 v, v dd2 = 5 v, t a = ?40 to 125 oc) parameter symbol test condition min typ max unit enable outputs t en1 t en2 typical input t plh t phl typical output t r t f 90% 10% 90% 10% 50% 50%
SI8430/31/35 rev. 0.3 7 table 2. electrical characteristics (v dd1 = 3.3 v, v dd2 = 3.3 v, t a = ?40 to 125 oc) parameter symbol test condition min typ max unit high level input voltage v ih 2.0 ? ? v low level input voltage v il ??0.8v high level output voltage v oh loh = ?4 ma v dd1 ,v dd2 ?0.4 3.1 ? v low level output voltage v ol lol = 4 ma ? 0.2 0.4 v input leakage current i l ??10a enable input high current i enh v enx = v ih ?4?a enable input low current i enl v enx = v il ?20?a dc supply current (all inputs 0 v or at supply) SI8430/35-a,-b,-c, v dd1 all inputs 0 dc ? 7 10 ma SI8430/35-a,-b,-c, v dd2 all inputs 0 dc ? 6 9 ma SI8430/35-a,-b,-c, v dd1 all inputs 1 dc ? 13 17 ma SI8430/35-a,-b,-c, v dd2 all inputs 1 dc ? 5 8 ma si8431-a,-b,-c, v dd1 all inputs 0 dc ? 7 11 ma si8431-a,-b,-c, v dd2 all inputs 0 dc ? 10 15 ma si8431-a,-b,-c, v dd1 all inputs 1 dc ? 12 18 ma si8431-a,-b,-c, v dd2 all inputs 1 dc ? 11 16 ma 10 mbps supply current (all inputs = 5 mhz square wave, ci = 15 pf on all outputs) SI8430/35-b,-c, v dd1 ?1014ma SI8430/35-b,-c, v dd2 ?1116ma si8431-b,-c, v dd1 ?1015ma si8431-b,-c, v dd2 ?1318ma 100 mbps supply current (all inputs = 50 mhz square wave, ci = 15 pf on all outputs) SI8430-c, v dd1 ?1115ma SI8430-c, v dd2 ?1620ma si8431-c, v dd1 ?1218ma si8431-c, v dd2 ?1925ma
SI8430/31/35 8 rev. 0.3 timing characteristics si843x-a maximum data rate 0 ? 1 mbps minimum pulse width ? ? 1000 ns propagation delay t phl , t plh see figure 2 ? ? 75 ns pulse width distortion |t plh - t phl | pwd see figure 2 ? ? 30 ns propagation delay skew 1 t psk(p-p) ? ? 50 ns channel-channel skew t psk ? ? 40 ns si843x-b maximum data rate 0 ? 10 mbps minimum pulse width ? ? 100 ns propagation delay t phl , t plh see figure 2 ? ? 35 ns pulse width distortion |t plh - t phl | pwd see figure 2 ? ? 7.5 ns propagation delay skew 1 t psk(p-p) ? ? 25 ns channel-channel skew t psk ??5ns si843x-c maximum data rate 0 ? 150 mbps minimum pulse width ? ? 6.6 ns propagation delay t phl , t plh see figure 2 4 6.5 9.5 ns pulse width distortion |t plh - t phl | pwd see figure 2 ? ? 3 ns propagation delay skew 1 t psk(p-p) ??5.5ns channel-channel skew t psk ??3ns table 2. electrical characteristics (continued) (v dd1 = 3.3 v, v dd2 = 3.3 v, t a = ?40 to 125 oc) parameter symbol test condition min typ max unit
SI8430/31/35 rev. 0.3 9 for all models output rise time t r c l = 15 pf see figure 2 ?2?ns output fall time t f c l = 15 pf see figure 2 ?2?ns common mode transient immunity ctmi v i =v dd or 0 v 25 30 ? kv/s enable to data valid t en1 see figure 1 ? 5 ? ns enable to data tri-state t en2 see figure 1 ? 5 ? ns start-up time 2 t su ?3?s notes: 1. t psk(p-p) is the magnitude of the difference in propagation de lay times measured between different units operating at the same supply voltages, l oad, and ambient temperature. 2. start-up time is the time period from the a pplication of power to valid data at the output. table 2. electrical characteristics (continued) (v dd1 = 3.3 v, v dd2 = 3.3 v, t a = ?40 to 125 oc) parameter symbol test condition min typ max unit
SI8430/31/35 10 rev. 0.3 table 3. electrical characteristics (v dd1 = 2.5 v, v dd2 = 2.5 v, t a = ?40 to 100 oc) parameter symbol test condition min typ max unit high level input voltage v ih 2.0 ? ? v low level input voltage v il ??0.8v high level output voltage v oh loh = ?4 ma v dd1 ,v dd2 ?0.4 2.3 ? v low level output voltage v ol lol = 4 ma ? 0.2 0.4 v input leakage current i l ??10a enable input high current i enh v enx = v ih ?4?a enable input low current i enl v enx = v il ?20?a dc supply current (all inputs 0 v or at supply) SI8430/35-a,-b,-c, v dd1 all inputs 0 dc ? 6 8 ma SI8430/35-a,-b,-c, v dd2 all inputs 0 dc ? 5 7 ma SI8430/35-a,-b,-c, v dd1 all inputs 1 dc ? 11 13 ma SI8430/35-a,-b,-c, v dd2 all inputs 1 dc ? 5 7 ma si8431-a,-b,-c, v dd1 all inputs 0 dc ? 7 10 ma si8431-a,-b,-c, v dd2 all inputs 0 dc ? 9 11 ma si8431-a,-b,-c, v dd1 all inputs 1 dc ? 11 13 ma si8431-a,-b,-c, v dd2 all inputs 1 dc ? 9 11 ma 10 mbps supply current (all inputs = 5 mhz square wave, ci = 15 pf on all outputs) SI8430/35-b,-c, v dd1 ?911ma SI8430/35-b,-c, v dd2 ?810ma si8431-b,-c, v dd1 ?911ma si8431-b,-c, v dd2 ?1013ma 100 mbps supply current (all inputs = 50 mhz square wave, ci = 15 pf on all outputs) SI8430-c, v dd1 ?1012ma SI8430-c, v dd2 ?1215ma si8431-c, v dd1 ?1215ma si8431-c, v dd2 ?1519ma
SI8430/31/35 rev. 0.3 11 timing characteristics si843x-a maximum data rate 0 ? 1 mbps minimum pulse width ? ? 1000 ns propagation delay t phl , t plh see figure 2 ? ? 75 ns pulse width distortion |t plh - t phl | pwd see figure 2 ? ? 30 ns propagation delay skew 1 t psk(p-p) ? ? 50 ns channel-channel skew t psk ? ? 40 ns si843x-b maximum data rate 0 ? 10 mbps minimum pulse width ? ? 100 ns propagation delay t phl , t plh see figure 2 ? ? 35 ns pulse width distortion |t plh - t phl | pwd see figure 2 ? ? 7.5 ns propagation delay skew 1 t psk(p-p) ? ? 25 ns channel-channel skew t psk ??5ns si843x-c maximum data rate 0 ? 100 mbps minimum pulse width ? ? 10 ns propagation delay t phl , t plh see figure 2 5 10 17 ns pulse width distortion |t plh - t phl | pwd see figure 2 ? ? 7 ns propagation delay skew 1 t psk(p-p) ? ? 12 ns channel-channel skew t psk ??4ns table 3. electrical characteristics (continued) (v dd1 = 2.5 v, v dd2 = 2.5 v, t a = ?40 to 100 oc) parameter symbol test condition min typ max unit
SI8430/31/35 12 rev. 0.3 for all models output rise time t r c l = 15 pf see figure 2 ?2?ns output fall time t f c l = 15 pf see figure 2 ?2?ns common mode transient immunity ctmi v i =v dd or 0 v 25 30 ? kv/s enable to data valid t en1 see figure 1 ? 5 ? ns enable to data tri-state t en2 see figure 1 ? 5 ? ns start-up time 2 t su ?3?s notes: 1. t psk(p-p) is the magnitude of the difference in propagation del ay times measured between different units operating at the same supply voltages, load, and ambient temperature. 2. start-up time is the time period from the a pplication of power to valid data at the output. table 3. electrical characteristics (continued) (v dd1 = 2.5 v, v dd2 = 2.5 v, t a = ?40 to 100 oc) parameter symbol test condition min typ max unit
SI8430/31/35 rev. 0.3 13 table 4. absolute maximum ratings parameter symbol min typ max unit storage temperature t stg ?65 ? 150 oc operating temperature t a ?40 ? 125 oc supply voltage v dd1 , v dd2 ?0.5 ? 6 v input voltage v i ?0.5 ? v dd + 0.5 v output voltage v o ?0.5 ? v dd + 0.5 v output current drive channel l o ??10ma lead solder temperature (10s) ? ? 260 oc maximum isolation voltage ? ? 4000 v dc note: permanent device damage may occur if the above absolute maximum ratings are exceeded. functional operation should be restricted to conditions as specified in the operational sections of this data sheet. table 5. recommended operating conditions parameter symbol test condition min typ max unit ambient operating temperature* t a 100 mbps, 15 pf, 5 v ?40 25 125 oc 150 mbps, 15 pf, 5 v 0 25 100 oc supply voltage v dd1 2.375 ? 5.5 v v dd2 2.375 ? 5.5 v *note: the maximum ambient temperature is dependent on data freque ncy, output loading, number of operating channels, and supply voltage.
SI8430/31/35 14 rev. 0.3 table 6. regulatory information csa the si84xx is certified under csa component acceptance notice. for more details, see file 232873. vde the si84xx is certified according to iec 60747-5-2. for more details, see file 5006301-4880-0001. ul the si84xx is certified under ul1577 component recogn ition program to provide basic insulation to 2500 v rms (1 minute). it is production tested > 3000 v rms for 1 second. for more details, see file e257455. table 7. insulation and safety-related specifications parameter symbol test condition value unit minimum air gap (clearance) l(io1) 7.7 min mm minimum external tracking (creepage) l(io2) 8.1 mm minimum internal gap (internal clearance) 0.008 min mm tracking resistance (comparative tracking index) cti din iec 60112/vde 0303 part 1 >175 v resistance (input-output) 1 r io 10 12 ? capacitance (input-output) 1 c io f=1mhz 1.4 pf input capacitance 2 c i 4.0 pf notes: 1. to determine resistance and capacitance, the si84xx is co nverted into a 2-terminal device. pins 1?8 are shorted together to form the first terminal and pins 9?16 are short ed together to form the second terminal. the parameters are then measured between these two terminals. 2. measured from input pin to ground.
SI8430/31/35 rev. 0.3 15 table 8. iec 60664-1 (vde 0884 part 2) ratings parameter test conditions specification basic isolation group material group iiia installation classification rated mains voltages < 150 v rms i-iv rated mains voltages < 300 v rms i-iii rated mains voltages < 400 v rms i-ii table 9. iec 60747-5-2 insulation characteristics* parameter symbol test condition characteristic unit maximum working insulation voltage v iorm 560 v peak input to output test voltage v pr method a after environmental tests subgroup 1 (v iorm x1.6=v pr , t m =60sec, partial discharge < 5 pc) 896 v peak method b1 (v iorm x1.875=v pr , 100% production test, t m =1 sec, partial discharge < 5 pc) 1050 after input and/or safety test subgroup 2/3 (v iorm x1.2=v pr , t m =60sec, partial discharge < 5 pc) 672 highest allowable overvoltage (transient overvoltage, t tr = 10 sec) v tr 4000 v peak pollution degree (din vde 0110, table 1) 2 insulation resistance at t s , v io =500v r s >10 9 ? *note: this isolator is suitable for basic electrical isolation only within the safety limit data. maintenance of the safety data is ensured by protective circuits. the si84xx pr ovides a climate classification of 40/125/21. table 10. iec safety limiting values parameter symbol test condition min typ max unit case temperature t s ? ? 150 c safety input, output, or supply current i s ja = 107 c/w, v i =5.5v, t j =150c, t a =25c ??210ma *note: maximum value allowed in the event of a failure; also see the thermal derating curve in figure 3 .
SI8430/31/35 16 rev. 0.3 figure 3. thermal derating curve, dependence of safety limiting values with case temperature per din en 60747-5-2 table 11. thermal characteristics parameter symbol test condition min typ max unit ic junction-to-case thermal resistance jc thermocouple located at center of package ?45?oc/w ic junction-to-air thermal resistance ja ?107?oc/w device power dissipation* p d ? ? 250 mw *note: the SI8430-c-is is tested with v dd1 =v dd2 =5.5v, t j =150oc, c l = 15 pf, input a 150 mbps 50% duty cycle square wave. 0 200 150 100 50 200 150 100 50 0 safety-limiting current (ma) 5.5 v 3.6 v 2.75 v 1 3 0 1 2 5 1 1 0 162 25 75 125 175
SI8430/31/35 rev. 0.3 17 2. typical performance characteristics figure 4. SI8430/35 typical v dd1 supply current vs. data rate 5, 3.3, and 2.5 v operation figure 5. SI8430/35 typical v dd2 supply current vs. data rate 5, 3.3, and 2.5 v operation (15 pf load) figure 6. si8431 typical v dd1 supply current vs. data rate 5, 3.3, and 2.5 v operation figure 7. si8431 typical v dd2 supply current vs. data rate 5, 3.3, and 2.5 v operation (15 pf load) 5 7 9 11 13 15 0 102030405060708090100 data rate (mbps) current (ma) 2.5v 5v 3.3v 0 5 10 15 20 25 0 102030405060708090100 data rate (mbps) current (ma) 2.5v 5v 3.3v 5 7 9 11 13 15 17 19 0 102030405060708090100 data rate (mbps) current (ma) 2.5v 5v 3.3v 5 7 9 11 13 15 17 19 0 102030405060708090100 data rate (mbps) current (ma) 2.5v 5v 3.3v
SI8430/31/35 18 rev. 0.3 figure 8. propagation delay vs. temperature 5 v operation figure 9. propagation delay vs. temperature 3.3 v operation figure 10. propagation delay vs. temperature 2.5 v operation 5 6 7 8 9 10 -40 -20 0 20 40 60 80 100 120 temperature (degrees c) delay (ns) rising edge falling edge 5 6 7 8 9 10 -40-20 0 20406080100120 temperature (degrees c) delay (ns) rising edge falling edge 5 7 9 11 13 15 -40-20 0 20406080100120 temperature (degrees c) delay (ns) falling edge rising edge
SI8430/31/35 rev. 0.3 19 3. application information 3.1. theory of operation the operation of an SI8430 channel is analogous to that of an opto coupler, except an rf carrier is modulated instead of light. this simple archit ecture provides a robust isolated data path and requires no special considerations or initialization at start-up. a simplified block diagram for a single SI8430 channel is shown in figure 11. a channel consists of an rf transmi tter and receiver separated by a transformer. referring to the transmitter, input a modulates the carrier provided by an rf oscillator using on/off keying and applies the resulting waveform to the primary of the tran sformer. the receiver contains a demodulator that decodes the input state according to its rf energy content and applies the result to output b via the output driver. figure 11. simplified channel diagram 3.2. eye diagram figure 12 illustrates an eye-diagram taken on an SI8430. the test us ed an anritsu (mp1763c) pulse pattern generator for the data source. the output of the generator's clock and data from an SI8430 were captured on an oscilloscope. the resu lts illustrate that data integrit y was maintained even at the hi gh data rate of 150 mbps. the results also show that very low pulse width distortion and very little jitter were exhibited. figure 12. eye diagram transmitter receiver rf oscillator modulator demodulator a b
SI8430/31/35 20 rev. 0.3 4. layout recommendations dielectric isolation is a set of specific ations produced by the safety regulatory agencies from around the world that describes the physical construction of electrical equipment that derives power from a high-voltage power system such as 100?240 v ac systems or industrial power systems. the dielec tric test (or hipot test) given in the safety specifications places a very high voltage between the input power pins of a product an d the user circuits and the user touchable surfaces of the product. for the iec rela ting to products deriving their power from the 220?240 v power grids, the test voltage is 2500 v ac (or 3750 v dc ?the peak equivalent voltage). there are two terms described in the safety specifications: creepage?the distance along the insulating surface an arc may travel. clearance?the distance through the shortest path through air that an arc may travel. figure 13 illustrates the accepted met hod of providing the pro per creepage distance along the surface. for a 220?240 v application, this distance is 8 mm and the wid e body soic package must be used. there must be no copper traces within this 8 mm exclusion area, and the surface should have a confor mal coating such as solder resist. the digital isolator chip must straddle this exclusion area. figure 13. creepage distance 4.1. supply bypass the si843x requires a 0.1 f bypass capacitor between v dd1 and gnd1 and v dd2 and gnd2. the capacitor should be placed as close as possible to the package.
SI8430/31/35 rev. 0.3 21 4.2. input and out put characteristics the si843x inputs and outputs are standard cmos driver s/receivers. the si844x inputs and outputs are standard cmos drivers/receivers. table 12 details powe red and unpowered operation of the si84xx. table 12. si84xx operation table v i input 1,2 en input 1,2,3,4 vddi state 1,5,6 vddo state 1,5,6 v o output 1,2 comments h h or nc p p h enabled, normal operation. lh or nc p p l x l p p hi-z disabled x h or nc up p l upon the transition of vddi from unpowered to powered, v o returns to the same state as v i in less than 1 s. x l up p hi-z disabled x x p up l upon the transition of vddi from unpowered to powered, v o returns to the same state as v i in less than 1 s, if en is in either the h or nc state. notes: 1. vddi and vddo are the input and output power supplies. v i and v o are the respective input and output terminals. en is the enable control input located on the same output side. 2. x = not applicable; h = logic high; l = logic low; hi-z = high impedance. 3. it is recommended that the enable inputs be connected to an external logic high or low level when the si84xx is operating in noisy environments. 4. no connect (nc) replaces en1 on SI8430/35. no connect r eplaces en2 on the si8435. no connects are not internally connected and can be left floating, tied to vdd, or tied to gnd. 5. "powered" state (p) is defined as 2.375 v < vdd < 5.5 v. 6. "unpowered" state (up) is defined as vdd = 0 v.
SI8430/31/35 22 rev. 0.3 4.3. enable (en1, en2) inputs enable inputs en1 and en2 can be used for multiplexing, for clock sync, or other outp ut control. en1, en2 logic operation is summarized for each isolator product in tabl e 13. these inputs are internally pulled-up to local vdd by a 9 a current source allowing them to be connected to an external logic level (high or low) or left floating. to minimize noise coupling, do not connect circuit traces to en1 or en2 if they are left floating. if en1, en2 are unused, it is recommended they be connec ted to an external logic level, especi ally if the si84xx is operating in a noisy environment. table 13. enable input truth table p/n en1* en2* operation SI8430 ? h outputs b1, b2, b3 are enabled. ? l outputs b1, b2, b3 are disabled and in high impedance state. si8431 h x output a3 enabled. l x output a3 disabled and in high impedance state. x h outputs b1, b2 are enabled. x l outputs b1, b2 are disabled and in high impedance state. si8435 ? ? outputs b1, b2, b3 are enabled. *note: x = not applicable; h = logic high; l = logic low.
SI8430/31/35 rev. 0.3 23 4.4. rf radiated emissions the SI8430 family uses a rf carrier frequency of appro ximately 2.1 ghz. this will re sult in a small amount of radiated emissions at this frequency and its harmonics. the radiation is not from the ic chip but due to a small amount of rf energy driving the isolated grou nd planes which can act as a dipole antenna. the unshielded SI8430 evaluation board passes f cc requirements. table 14 shows measured emissions compared to fcc requirements. radiated emissions can be reduced if the circuit board is enclosed in a shielded enclosure or if the pcb is a less efficient antenna. table 14. radiated emissions frequency (ghz) measured (dbv/m) fcc spec (dbv/m) compared to spec (db) 2.094 70.0 74.0 ?4.0 2.168 68.3 74.0 ?5.7 4.210 61.9 74.0 ?12.1 4.337 60.7 74.0 ?13.3 6.315 58.3 74.0 ?15.7 6.505 60.7 74.0 ?13.3 8.672 45.6 74.0 ?28.4
SI8430/31/35 24 rev. 0.3 4.5. rf immunity and comm on mode transient immunity the SI8430 family has very high common mode transient immunity while transmitting data. this is typically measured by applying a square pulse with very fast ri se/fall times between the isolated grounds. measurements show no failures up to 30 kv/s. during a high surge even t the output may glitch low for up to 20?30 ns, but the output corrects immediately after the surge event. the si843x family passes the industrial requirements of cispr24 for rf immunity of 3 v/m using an unshielded evaluation board. as shown in figure 14, the isolated ground planes form a parasitic dipole antenna, while figure 15 shows the rms common mode voltage versus frequency above which the si843x becomes susceptible to data corruption. to avoid compromising data, care must be taken to keep rf common-mode voltage below the envelope specified in figure 15. the pcb should be laid-out to not act as an efficient antenna for the rf frequency of interest. rf su sceptibility is also significantly reduced when the e nd system is housed in a metal enclosure, or otherwise shielded. figure 14. dipole antenna figure 15. rms common mode voltage vs. frequency isolator gnd1 gnd2 dipole antenna 0 1 2 3 4 5 500 1000 1500 2000 frequency (mhz) rms voltage (v)
SI8430/31/35 rev. 0.3 25 5. pin descriptions name soic-16 pin# type description v dd1 1 supply side 1 power supply. gnd1 2 ground side 1 ground. a1 3 digital input side 1 digital input. a2 4 digital input side 1 digital input. a3 5 digital i/o side 1 digital input or output. nc 6 na no connect. en1/nc* 7 digital input side 1 active high enable. nc on SI8430/35 gnd1 8 ground side 1 ground. gnd2 9 ground side 2 ground. en2/nc* 10 digital input side 2 active high enable. nc on si8435. nc 11 na no connect. b3 12 digital i/o side 2 digital input or output. b2 13 digital output side 2 digital output. b1 14 digital output side 2 digital output. gnd2 15 ground side 2 ground. v dd2 16 supply side 2 power supply. *note: no connect. these pins are not internally connected. th ey can be left floating, tied to vdd or tied to gnd. wide body soic v dd1 gnd1 a1 a3 nc en1/nc gnd1 a2 1 2 3 4 5 6 7 8 top view v dd2 gnd2 b2 b1 nc b3 gnd2 en2/nc 9 12 11 10 13 14 15 16
SI8430/31/35 26 rev. 0.3 6. ordering guide ordering part number number of inputs v dd1 side number of inputs v dd2 side maximum data rate temperature package type SI8430-a-is 3 0 1 ?40 to 125 c soic-16 SI8430-b-is 3 0 10 ?40 to 125 c soic-16 SI8430-c-is 3 0 150 ?40 to 125 c soic-16 si8431-a-is 2 1 1 ?40 to 125 c soic-16 si8431-b-is 2 1 10 ?40 to 125 c soic-16 si8431-c-is 2 1 150 ?40 to 125 c soic-16 si8435-b-is 3 0 10 ?40 to 125 c soic-16 note: all packages are pb-free and rohs compliant. moisture sens itivity level is msl2 with peak reflow temperature of 260 c according to the jedec industry standard cl assifications, and peak solder temperature.
SI8430/31/35 rev. 0.3 27 7. package outline: wide body soic figure 16 illustrates the package details for the quad -channel digital isolator. tabl e 14 lists the values for the dimensions shown in the illustration. figure 16. 16-pin wide body soic table 14. package diagram dimensions symbol millimeters min max a ? 2.65 a1 0.1 0.3 d 10.3 bsc e 10.3 bsc e1 7.5 bsc b 0.31 0.51 c 0.20 0.33 e 1.27 bsc h 0.25 0.75 l 0.4 1.27 0 7
SI8430/31/35 28 rev. 0.3 d ocument c hange l ist revision 0.1 to revision 0.11 updated table 7, ?regulatory information,? on page 14. minor typographical edits. revision 0.11 to revision 0.2 updated supply current specifications in table 1, ?electrical characteristics,? on page 4, table 2, ?electrical characteristics,? on page 7, and table 3, ?electrical characteristics,? on page 10. updated performance plots in figures 4, 5, 6, and 7. added nc note (note 3) to table 10, ?si84xx truth table (positive logic),? on page 16. added nc note (*) to "5. pin descriptions" on page 25. revision 0.2 to revision 0.3 updated notes to tables 1, 2, & 3. updated figure 2. updated tables 6?11 to clarify specifications, test limits, & device characteristics.
SI8430/31/35 rev. 0.3 29 n otes :
SI8430/31/35 30 rev. 0.3 c ontact i nformation silicon laboratories inc. 400 west cesar chavez austin, tx 78701 tel: 1+(512) 416-8500 fax: 1+(512) 416-9669 toll free: 1+(877) 444-3032 email: powerproducts@silabs.com internet: www.silabs.com silicon laboratories and silicon labs are trademarks of silicon laboratories inc. other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders. the information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. silicon laboratories assumes no responsibility for errors and omissions, and disclaims responsib ility for any consequences resu lting from the use of information included herein. a dditionally, silicon laboratorie s assumes no responsibility for the functioning of und escribed features or parameters. silicon laboratories reserves the right to make changes without further notice . silicon laboratories makes no wa rranty, rep- resentation or guarantee regarding the suitability of its products for any particular purpose, nor does silicon laboratories as sume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any an d all liability, including wi thout limitation conse- quential or incidental damages. silicon laborat ories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the silicon labor atories product could create a s ituation where per- sonal injury or death may occur. should buyer purchase or us e silicon laboratories products for any such unintended or unauthor ized ap- plication, buyer shall indemnify and hold silicon laboratories harmless against all claims and damages.

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